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</style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - FIR Compiler v13.1</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>fir_lowpass_ast</TD></TR><TR><TD><B>Variation Name</B></TD><TD>fir_lowpass</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>D:\project\FPGA\Verilog_maxboss\46_FIR_audio_lcd\par\ipcore\FIR</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>fir_lowpass.v</TD><TD>A MegaCore<small><sup>&reg</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function.  Instantiate the entity defined by this file inside of  your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>fir_lowpass_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function  variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>fir_lowpass.bsf</TD><TD>Quartus<small><sup>&reg</sup></small> II symbol file for the MegaCore function variation.  You can use this file in the Quartus  II block diagram editor.</TD></TR><TR><TD>fir_lowpass_ast.vhd</TD><TD>The wrapper file for Avalon Streaming Interface.</TD></TR><TR><TD>fir_lowpass_constraints.tcl</TD><TD>Constraints setting file for Quartus II synthesis. This file contains the necessary constraints to achieve FIR Filter size and speed.</TD></TR><TR><TD>fir_lowpass_nativelink.tcl</TD><TD>A Tcl script that can be used to assign NativeLink simulation testbench settings to the Quartus II project.</TD></TR><TR><TD>fir_lowpass_mlab.m</TD><TD>A MATLAB M-File.  This file provides the kernel of the MATLAB simulation model for the customized FIR Variant.</TD></TR><TR><TD>fir_lowpass_model.m</TD><TD>A MATLAB M-File.  This file provides a MATLAB simulation model for the customized FIR Variant. IT makes use of the <your_fir_variant>_mlab.m file.</TD></TR><TR><TD>fir_lowpass.vec</TD><TD>Quartus II Vector file.  This file provides simulation test vectors to be used simulating the customized FIR Variant with the Quartus II software.</TD></TR><TR><TD>tb_fir_lowpass.vhd</TD><TD>A VHDL file. This file provides a VHDL testbench for the customized FIR Variant.</TD></TR><TR><TD>fir_lowpass_msim.tcl</TD><TD>A Tcl file.  This file provides a Tcl script to simulate the HDL testbench together with the simulation model of customized FIR Variant.</TD></TR><TR><TD>fir_lowpass_input.txt</TD><TD>A text file.  This file provides simulation data for the MATLAB model and the simulation testbench.</TD></TR><TR><TD>fir_lowpass_coef_int.txt</TD><TD>A text file.  This file provides coefficient input file for MATLAB testbench.</TD></TR><TR><TD>fir_lowpass_param.txt</TD><TD>A text file.  This file record all output parameters for customized FIR variant.</TD></TR><TR><TD>fir_lowpass_silent_param.txt</TD><TD>A text file.  This file record all input parameters for customized FIR variant.</TD></TR><TR><TD>fir_lowpass.qip</TD><TD>Contains Quartus II project information for your MegaCore function variation.</TD></TR><TR><TD>fir_lowpass.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width="75%"><TR align="left"><TH align="left"><B>Name</B></TH><TH align="left"><B>Direction</B></TH><TH align="left"><B>Width</B></TH></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ast_sink_data</TD><TD>INPUT</TD><TD>16</TD></TR><TR><TD>ast_source_data</TD><TD>OUTPUT</TD><TD>34</TD></TR><TR><TD>ast_sink_valid</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ast_sink_ready</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ast_source_valid</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ast_source_ready</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ast_sink_error</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ast_source_error</TD><TD>OUTPUT</TD><TD>2</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>